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arm64: dts: r8a7796: Add CA53 L2 cache-controller node
authorGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 7 Mar 2017 18:03:24 +0000 (19:03 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Fri, 10 Mar 2017 09:26:43 +0000 (10:26 +0100)
commita681e6d63285b879bb9bab0bd79e2021e6dcbda1
tree14886e1a124ff05f6537df341bdf3497d7c00e3ftree | snapshot (tar.gz zip)
parent9fccf4d6103eeb5db88c1ae026d61b87f722414acommit | diff
arm64: dts: r8a7796: Add CA53 L2 cache-controller node

Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Extracted from a patch by Takeshi Kihara in the BSP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm64/boot/dts/renesas/r8a7796.dtsi diff | blob | blame | history