KVM: x86: do mask out upper bits of PAE CR3
authorPaolo Bonzini <pbonzini@redhat.com>
Mon, 24 Jul 2017 16:54:38 +0000 (18:54 +0200)
committerPaolo Bonzini <pbonzini@redhat.com>
Wed, 26 Jul 2017 16:57:45 +0000 (18:57 +0200)
commita512177ef3bb92dbec8a96fe337b11c126bf9c91
tree6e141e2fb56dfd3c6f856d8e3d7e5bdcfae8aff3
parentfdeaf7e3eb37c6dbc4b4ac97dbe1945d239eb788
KVM: x86: do mask out upper bits of PAE CR3

This reverts the change of commit f85c758dbee54cc3612a6e873ef7cecdb66ebee5,
as the behavior it modified was intended.

The VM is running in 32-bit PAE mode, and Table 4-7 of the Intel manual
says:

Table 4-7. Use of CR3 with PAE Paging
Bit Position(s) Contents
4:0 Ignored
31:5 Physical address of the 32-Byte aligned
page-directory-pointer table used for linear-address
translation
63:32 Ignored (these bits exist only on processors supporting
the Intel-64 architecture)

To placate the static checker, write the mask explicitly as an
unsigned long constant instead of using a 32-bit unsigned constant.

Cc: Dan Carpenter <dan.carpenter@oracle.com>
Fixes: f85c758dbee54cc3612a6e873ef7cecdb66ebee5
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
arch/x86/kvm/x86.c