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ARM: perf: add mode exclusion for Cortex-A15 PMU
authorWill Deacon <will.deacon@arm.com>
Tue, 19 Jul 2011 12:53:36 +0000 (13:53 +0100)
committerWill Deacon <will.deacon@arm.com>
Wed, 31 Aug 2011 09:18:01 +0000 (10:18 +0100)
commita505addc366525cd8d9358298be0dc8655be5953
tree3a2fcfc4ed7659bed5743558ec2fcd937dfa889ctree | snapshot (tar.gz zip)
parent05d22fde3c0b86c8395d8f12ac01fbbc524d73cacommit | diff
ARM: perf: add mode exclusion for Cortex-A15 PMU

The Cortex-A15 PMU implements the PMUv2 specification and therefore
has support for some mode exclusion.

This patch adds support for excluding user, kernel and hypervisor counts
from a given event.

Acked-by: Jamie Iles <jamie@jamieiles.com>
Reviewed-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
arch/arm/kernel/perf_event_v7.c diff | blob | blame | history
Motorola kernel-slsi