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ASoC: Intel: cht_bsw_rt5645: add Baytrail MCLK support
authorPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Thu, 26 Jan 2017 20:09:38 +0000 (14:09 -0600)
committerMark Brown <broonie@kernel.org>
Tue, 31 Jan 2017 20:03:56 +0000 (20:03 +0000)
commita50477e55fff69e1028f25624ee9fc9182d59b1f
tree7dd6af7e656b9e879f506f825dbb1e744fb59b7ctree | snapshot (tar.gz zip)
parent39d75485689de9abd2b27e9b2771c48db8e4be23commit | diff
ASoC: Intel: cht_bsw_rt5645: add Baytrail MCLK support

The existing code assumes a 19.2 MHz MCLK as the default
hardware configuration. This is valid for CherryTrail but
not for Baytrail.

Add explicit MCLK configuration to set the 19.2 clock on/off
depending on DAPM events.

This is a prerequisite step to enable devices with Baytrail
and RT5645 such as Asus X205TA

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/intel/boards/cht_bsw_rt5645.c diff | blob | blame | history
Motorola kernel-slsi