drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 26 Jan 2012 16:18:47 +0000 (17:18 +0100)
committerKeith Packard <keithp@keithp.com>
Sun, 29 Jan 2012 01:37:42 +0000 (17:37 -0800)
commita4ea430853b71753103ec693acfc8624bd3e748e
tree3933fb384e1b65b52b056aae5e3c1a86b7ff68af
parentd56d8b28e9247e7e35e02fbb12b12239a2c33ad1
drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT

An identical patch has been merged for i9xx_crtc_mode_set:

Commit 59df7b1771c150163e522f33c638096ab0efbf42
Author: Christian Schmidt <schmidt@digadd.de>
Date:   Mon Dec 19 20:03:33 2011 +0100

    drm/intel: Fix initialization if startup happens in interlaced mode [v2]

But that one neglected to fix up the ironlake+ path.

This should fix the issue reported by Alfonso Fiore where booting with
only a HDMI cable connected to his TV failed to display anything. The
issue is that the bios set up things for 1080i and used the pannel
fitter to scale up the lower progressive resolutions. We failed to
clear the interlace bit in the PIPEACONF register, resulting in havoc.

Cc: Peter Ross <pross@xvid.org>
Tested-by: Alfonso Fiore <alfonso.fiore@gmail.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
drivers/gpu/drm/i915/intel_display.c