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(parent: 7ce7d89) | patch
clk: sunxi-ng: fix PLL_CPUX adjusting on H3
authorOndrej Jirman <megous@megous.com>
Fri, 25 Nov 2016 00:28:47 +0000 (01:28 +0100)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Mon, 2 Jan 2017 21:24:55 +0000 (22:24 +0100)
commita43c96427e713bea94e9ef50e8be1f493afc0691
tree64d672ed9bd3c1e371b29d323eceb51aa9f870f4tree | snapshot (tar.gz zip)
parent7ce7d89f48834cefece7804d38fc5d85382edf77commit | diff
clk: sunxi-ng: fix PLL_CPUX adjusting on H3

When adjusting PLL_CPUX on H3, the PLL is temporarily driven
too high, and the system becomes unstable (oopses or hangs).

Add a notifier to avoid this situation by temporarily switching
to a known stable 24 MHz oscillator.

Signed-off-by: Ondrej Jirman <megous@megous.com>
Tested-by: Lutz Sammer <johns98@gmx.net>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu-sun8i-h3.c diff | blob | blame | history