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powerpc/bpf: Fix DIVWU instruction opcode
authorVladimir Murzin <murzin.v@gmail.com>
Sat, 28 Sep 2013 08:22:00 +0000 (10:22 +0200)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Thu, 31 Oct 2013 05:19:20 +0000 (16:19 +1100)
commita40a2b670706494610d794927b9aebe77e18af8d
tree02b94031e1dc501e3ade7bb93908705006d2ee57tree | snapshot (tar.gz zip)
parenta3e31b4588443f37d82195096c6b30dff1c152c2commit | diff
powerpc/bpf: Fix DIVWU instruction opcode

Currently DIVWU stands for *signed* divw opcode:

7d 2a 4b 96  divwu   r9,r10,r9
7d 2a 4b d6  divw    r9,r10,r9

Use the *unsigned* divw opcode for DIVWU.

Suggested-by: Vassili Karpov <av1474@comtv.ru>
Reviewed-by: Vassili Karpov <av1474@comtv.ru>
Signed-off-by: Vladimir Murzin <murzin.v@gmail.com>
Acked-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/include/asm/ppc-opcode.h diff | blob | blame | history