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ASoC: wm8960: Fix PLL register writes
authorMike Dyer <mike.dyer@md-soft.co.uk>
Fri, 16 Aug 2013 17:36:28 +0000 (18:36 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 27 Sep 2013 00:18:13 +0000 (17:18 -0700)
commita1b8ce5ac7db6a7c29a4ca658d5aff5384bd073e
tree02501896dd505436ea5f08400b9be8c7f649e804tree | snapshot (tar.gz zip)
parent215840ab83bfdd15deca0a8b0f140369afab7f52commit | diff
ASoC: wm8960: Fix PLL register writes

commit 85fa532b6ef920b32598df86b194571a7059a77c upstream.

Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part
should be split across each register in 8bit chunks.

Signed-off-by: Mike Dyer <mike.dyer@md-soft.co.uk>
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
sound/soc/codecs/wm8960.c diff | blob | blame | history
kernel source for telekom puls (alcatel/mediatek)