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(parent: 6a46cd4) | patch
gpu: ipu-v3: Fix i.MX51 CSI control registers offset
authorAlexander Shiyan <shc_work@mail.ru>
Thu, 20 Dec 2018 08:06:38 +0000 (11:06 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 23 Mar 2019 13:35:10 +0000 (14:35 +0100)
commita0e11262c67ef2eb75f93651643fb8345ab282c4
tree01da05973f8381d40eb09947220373d99f2127e4tree | snapshot (tar.gz zip)
parent6a46cd4abe4f6f7be3b6004031ce36e9c9e30478commit | diff
gpu: ipu-v3: Fix i.MX51 CSI control registers offset

[ Upstream commit 2c0408dd0d8906b26fe8023889af7adf5e68b2c2 ]

The CSI0/CSI1 registers offset is at +0xe030000/+0xe038000 relative
to the control module registers on IPUv3EX.
This patch fixes wrong values for i.MX51 CSI0/CSI1.

Fixes: 2ffd48f2e7 ("gpu: ipu-v3: Add Camera Sensor Interface unit")

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/ipu-v3/ipu-common.c diff | blob | blame | history