drm/i915: Align "unfenced" tiled access on gen2, early gen3
authorChris Wilson <chris@chris-wilson.co.uk>
Sat, 25 Mar 2017 11:32:43 +0000 (11:32 +0000)
committerJani Nikula <jani.nikula@intel.com>
Wed, 29 Mar 2017 10:52:08 +0000 (13:52 +0300)
commit9e1764309f577a88a0d5250fea6a080a6ad43556
tree646f45a688f1fe1a545ce23b8a3aef70796cf5e8
parent0abfe7e2570d7c729a7662e82c09a23f00f29346
drm/i915: Align "unfenced" tiled access on gen2, early gen3

Old devices have quite severe restrictions for using fences, and unlike
more recent device (anything from Pineview onwards) we need to enforce
those restrictions even for unfenced tiled access from the render
pipeline.

Fixes: 944397f04f24 ("drm/i915: Store required fence size/alignment for GGTT vma")
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: <drm-intel-fixes@lists.freedesktop.org> # v4.11-rc1+
Link: http://patchwork.freedesktop.org/patch/msgid/20170325113243.16438-1-chris@chris-wilson.co.uk
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
(cherry picked from commit f4ce766f28cd0efa0cb4d869a84905d573ef7e70)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem_execbuffer.c
drivers/gpu/drm/i915/i915_pci.c