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[ARM] 4128/1: Architecture compliant TTBR changing sequence
authorCatalin Marinas <catalin.marinas@arm.com>
Mon, 5 Feb 2007 13:47:40 +0000 (14:47 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Thu, 8 Feb 2007 14:49:24 +0000 (14:49 +0000)
commit9d99df4b10eef130dacb5f772cd589c625b03634
treebf1cea618ef9380cdce9cfea8897da9fb961787btree | snapshot (tar.gz zip)
parent620879c9e33262426db0ade650be5d7a2046377bcommit | diff
[ARM] 4128/1: Architecture compliant TTBR changing sequence

On newer architectures (ARMv6, ARMv7), the depth of the prefetch and
branch prediction is implementation defined and there is a small risk
of wrong ASID tagging when changing TTBR0 before setting the new
context id. The recommended solution is to set a reserved ASID during
TTBR changing. This patch reserves ASID 0.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mm/context.c diff | blob | blame | history
kernel source for telekom puls (alcatel/mediatek)