clk: samsung: exynos7: add gate clock for DMA block
authorPadmavathi Venna <padma.v@samsung.com>
Tue, 13 Jan 2015 11:27:40 +0000 (16:57 +0530)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Thu, 15 Jan 2015 14:11:40 +0000 (15:11 +0100)
commit9cc2a0c95ff3f815deeba1ccd0d11b1d3bc46551
tree554a4e642438b0ccdeff9f7b4e0b9708083afb78
parent83f191a7cdf5286a8f3745e847f50c29fa349da9
clk: samsung: exynos7: add gate clock for DMA block

Add support for PDMA0 and PDMA1 gate clks.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos7.c
include/dt-bindings/clock/exynos7-clk.h