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(parent: 84b046f) | patch
drm/i915: Set PIPECONF color range bit on Valleyview
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 2 Apr 2013 13:10:09 +0000 (16:10 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 5 Apr 2013 18:47:20 +0000 (20:47 +0200)
commit9c8e09b7a551fc81842a2d9cdc3e42a5b729820f
treebb3d1dd24b775960ab4dc554ce93e7f56e37d536tree | snapshot (tar.gz zip)
parent84b046f3985357a040721affebff8603264d793ecommit | diff
drm/i915: Set PIPECONF color range bit on Valleyview

VLV has the color range selection bit in the PIPECONF register.
Configure it appropriately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: fixup rebase issues due to slightly different baseline.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c diff | blob | blame | history
Motorola kernel-slsi