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MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation
authorMaciej W. Rozycki <macro@linux-mips.org>
Wed, 27 May 2015 13:15:20 +0000 (14:15 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Sun, 21 Jun 2015 19:52:41 +0000 (21:52 +0200)
commit9a20b09285bbd75ccc2ca78233241f8e31d54a28
treef18914b5a7e902428a14a9b58025d64ff950d64etree | snapshot (tar.gz zip)
parent3bcb03f3a7160e411c5f335028a5c70b32f0edb7commit | diff
MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation

Replace an explicit barrier with a useful processor instruction in TLB
invalidation, following several other such cases elsewhere in
`tlb-r3k.c'.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10196/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mm/tlb-r3k.c diff | blob | blame | history