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(parent: 7dfa4b4) | patch
net/mlx4_en: Align tx path structures to cache lines
authorEric Dumazet <edumazet@google.com>
Sun, 5 Oct 2014 09:35:10 +0000 (12:35 +0300)
committerDavid S. Miller <davem@davemloft.net>
Mon, 6 Oct 2014 05:04:15 +0000 (01:04 -0400)
commit98b1634941e3efb0334f794efc79702839993d86
treed5cc5f5e6fd9984c3ec59652de96fe9824157d22tree | snapshot (tar.gz zip)
parent7dfa4b414d4eec8da56e44fb2b4aea3e549b092fcommit | diff
net/mlx4_en: Align tx path structures to cache lines

Reorganize struct mlx4_en_tx_ring to have:
- One cache line containing last_nr_txbb & cons & wake_queue, used by tx
  completion.
- One cache line containing fields dirtied by mlx4_en_xmit()
- Following part is read mostly and shared by cpus.

Align struct mlx4_en_tx_info to a cache line

Signed-off-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: Amir Vadai <amirv@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/mellanox/mlx4/mlx4_en.h diff | blob | blame | history