drm/i915/glk: limit pixel clock to 99% of cdclk workaround

drm/i915/glk: limit pixel clock to 99% of cdclk workaround

As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
Practically we can achive only 99% of these cdclk values (HW team
checking on this). So cdclk should be calculated for the given pixclk as
per that otherwise it may lead to screen corruption, explained below:
1. For DSI AUO panel(1920x1200 @60) required pixclk is 157100 KHZ
2. glk_calc_cdclk returns 79200 KHZ for this pixclk, For 2PPC it
   will be 158400 KHZ
3. Practically 100% of the cdclk can’t be achieved, so 99% of 158400
   KHZ  = 156816 which is less than the desired pixlclk and causes
   panel corruption.

v2: Rebased to new CDLCK code framework
v3: Addressed review comments from Ander/Jani
    - Add comment in code about 99% usage of CDCLK
    - Calculate max dot clock as well with 99% limit
v4 by Jani:
    - drop superfluous whitespace change
    - rewrite code comments to clarify
v5: Added details of non-working scenario in commit message

Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1491397463-13637-1-git-send-email-madhav.chauhan@intel.com