MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs
authorGabor Juhos <juhosg@openwrt.org>
Sat, 8 Sep 2012 12:02:21 +0000 (14:02 +0200)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 1 Oct 2012 09:37:15 +0000 (11:37 +0200)
commit97541ccfb9db2bb9cd1dde6344d5834438d14bda
treefbdcb943e76ee180c6025a2f7f5645c101014f00
parent65fc7f9957c52ad4fdf4ee5dfe3a75aa0a633d39
MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs

Besides the CPU and DDR PLLs, the CPU and DDR frequencies
can be derived from other PLLs in the SRIF block on the
AR934x SoCs. The current code does not checks if the SRIF
PLLs are used and this can lead to incorrectly calculated
CPU/DDR frequencies.

Fix it by calculating the frequencies from SRIF PLLs if
those are used on a given board.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: <stable@vger.kernel.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4324/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/ath79/clock.c
arch/mips/include/asm/mach-ath79/ar71xx_regs.h