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(parent: 2893c37) | patch
clk: mediatek: Add initial common clock support for Mediatek SoCs.
authorJames Liao <jamesjj.liao@mediatek.com>
Thu, 23 Apr 2015 08:35:39 +0000 (10:35 +0200)
committerStephen Boyd <sboyd@codeaurora.org>
Wed, 6 May 2015 05:50:31 +0000 (22:50 -0700)
commit9741b1a68035b541005db1a4d7623bd9b3522ab4
treed78897587e33ebb5d6a38a62bed6935adbf840bdtree | snapshot (tar.gz zip)
parent2893c379461a208b3059f55dfe4dafa06b4aa46acommit | diff
clk: mediatek: Add initial common clock support for Mediatek SoCs.

This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
[sboyd@codeaurora.org: Squelch checkpatch warning in clk-mtk.h]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/Makefile diff | blob | blame | history
drivers/clk/mediatek/Makefile [new file with mode: 0644] blob
drivers/clk/mediatek/clk-gate.c [new file with mode: 0644] blob
drivers/clk/mediatek/clk-gate.h [new file with mode: 0644] blob
drivers/clk/mediatek/clk-mtk.c [new file with mode: 0644] blob
drivers/clk/mediatek/clk-mtk.h [new file with mode: 0644] blob
drivers/clk/mediatek/clk-pll.c [new file with mode: 0644] blob