clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output
authorChen-Yu Tsai <wens@csie.org>
Wed, 12 Nov 2014 18:08:31 +0000 (02:08 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Sun, 23 Nov 2014 16:02:56 +0000 (17:02 +0100)
commit95e94c1fadcd1959857db45c2e11810a893badd0
tree2c62bbbe6df23b6b1ab8bb5660d06dc3384a58fd
parent13d52f61065dcdbea13aae2f0aea6af43a3abf65
clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output

Some clock modules on the A31 use PLL6x2 as one of their inputs.
This patch changes the PLL6 implementation for A31 to a divs clock,
i.e. clock with multiple outputs that have different dividers.
The first output will be the normal PLL6 output, and the second
will be PLL6x2.

This patch fixes the PLL6 N factor in the clock driver, and removes
any /2 dividers in the PLL6 factors clock part. The N factor counts
from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Documentation/devicetree/bindings/clock/sunxi.txt
drivers/clk/sunxi/clk-sunxi.c