spi: fsl-dspi: Add ~50ns delay between cs and sck
authorAaron Brice <aaron.brice@datasoft.com>
Fri, 3 Apr 2015 20:39:31 +0000 (13:39 -0700)
committerMark Brown <broonie@kernel.org>
Mon, 6 Apr 2015 17:12:25 +0000 (18:12 +0100)
commit95bf15f386417f3ba80bb860c1385b1ebfdcdffa
tree61b3f2885d7c8f8d3a7cbe2c36fd1bd7b001498a
parentc1c14957afd3026dcbc2e7ca599e6d035c7d8e01
spi: fsl-dspi: Add ~50ns delay between cs and sck

Add delay between chip select and clock signals, before clock starts and
after clock stops.

Signed-off-by: Aaron Brice <aaron.brice@datasoft.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-fsl-dspi.c