drm/i915: update BDW DDI buffer translations
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Fri, 13 Jun 2014 21:45:40 +0000 (18:45 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 16 Jun 2014 17:57:05 +0000 (19:57 +0200)
commit9576c27f5287f873505583350049100896a48299
treea0aedea3da4bed44dea445d26d40a76df07eea0d
parent1ce826d436f33c8fc0cf8b51d213b496ea73e0a6
drm/i915: update BDW DDI buffer translations

Two BSpec updates changed the recommended values for BDW eDP and DP
DDI buffer translations. Now the signal levels also match the HSW signal
levels, which simplify things a little bit.

It seems some DP sinks don't work properly without voltage level 0 and
pre-emphasis level 3, so this patch may fix some bugs on
panels/monitors that happen on BDW but not on HSW.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ddi.c
drivers/gpu/drm/i915/intel_dp.c