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drm/i915: Set aux clk to 100MHz for Valleyview
authorVijay Purushothaman <vijay.a.purushothaman@intel.com>
Thu, 27 Sep 2012 13:43:01 +0000 (19:13 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 28 Sep 2012 14:42:52 +0000 (16:42 +0200)
commit9473c8f485e1e3740d5aebf1de4838b615f9dedc
tree545c8f135d6f3ef81fd027811d28ce21b1cd347ctree | snapshot (tar.gz zip)
parent3bcedbe5f2a3da65326d99803cac71c1e89bc93fcommit | diff
drm/i915: Set aux clk to 100MHz for Valleyview

Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_dp.c diff | blob | blame | history