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(parent: a42f704) | patch
drm/i915: HSW PM Frequency bits fix
authorRodrigo Vivi <rodrigo.vivi@gmail.com>
Mon, 25 Mar 2013 20:55:49 +0000 (17:55 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 26 Mar 2013 08:04:01 +0000 (09:04 +0100)
commit92bd1bf089762dfee9fe34437068714a881c8bc0
tree2af7851320c1c2a2214fc1e4f0a97f677a951e53tree | snapshot (tar.gz zip)
parenta42f704b71b252705f34fbe60ea6f4a76f891a78commit | diff
drm/i915: HSW PM Frequency bits fix

According to HSW PM programming guide, frequency bits starts at
24 instead of 25.

v2: Paulo Zanoni noticed that only frequency bits can be set at
GEN6_RPNSWREQ. All others are read only.

CC: Ben Widawsky <ben@bwidawsk.net>
CC: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | blame | history
drivers/gpu/drm/i915/intel_pm.c diff | blob | blame | history