drm/i915/bdw: Check for slice, subslice and EU count for BDW
authorŁukasz Daniluk <lukasz.daniluk@intel.com>
Fri, 25 Sep 2015 09:54:58 +0000 (11:54 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 30 Sep 2015 12:13:03 +0000 (14:13 +0200)
commit91bedd34abf0cd3f6276de642a145f75731acca5
treed1d66f3ca2d0a90e2cc8c3b952b90cbd3690f580
parent76b1cf211cbe120a2d6c46403abc97d4376c619e
drm/i915/bdw: Check for slice, subslice and EU count for BDW

Added checks for available slices, subslices and EUs for Broadwell. This
information is filled in intel_device_info and is available to user with
GET_PARAM.
Added checks for enabled slices, subslices and EU for Broadwell. This
information is based on available counts but takes power gated slices
into account. It can be read in debugfs.
Introduce new register defines that contain information on slices on
Broadwell.

v2:
- Introduce GT_SLICE_INFO register
- Change Broadwell sseu_device_status function to use GT_SLICE_INFO
  register instead of RPCS register
- Undo removal of dev_priv variables in Cherryview and Gen9
  sseu_device_satus functions

v3:
- Fix style issues

v4:
- Corrected comment
- Reverted reordering of defines

Cc: Jeff Mcgee <jeff.mcgee@intel.com>
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Łukasz Daniluk <lukasz.daniluk@intel.com>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_reg.h