clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
authorIcenowy Zheng <icenowy@aosc.io>
Sun, 23 Jul 2017 10:27:45 +0000 (18:27 +0800)
committerChen-Yu Tsai <wens@csie.org>
Fri, 4 Aug 2017 04:05:33 +0000 (12:05 +0800)
commit913c3d85b4b562e38242765baa95113c8c7f1c14
tree1a0d0326366d15eb0bd06b8ba60de24ea4277f2c
parent48d5eb619c15847aba6757deb5c2c8badca2aece
clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3

The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
can be adjusted by changing the frequency of the PLL_CPUX clock.

Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
clock can be adjusted when adjusting the CPUX clock.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
drivers/clk/sunxi-ng/ccu-sun8i-h3.c