pstore/core: drop cmpxchg based updates
authorSebastian Andrzej Siewior <bigeasy@linutronix.de>
Thu, 8 Sep 2016 11:48:06 +0000 (13:48 +0200)
committerWilly Tarreau <w@1wt.eu>
Fri, 10 Feb 2017 10:04:01 +0000 (11:04 +0100)
commit90efe9d4773eedf96d9e4ebb0193da7c6f09ca52
tree05eb3820a8a7ddc0f82d41575997f072b8f290e6
parent98af342bf574c0fb71194be847014cf3ac90737b
pstore/core: drop cmpxchg based updates

commit d5a9bf0b38d2ac85c9a693c7fb851f74fd2a2494 upstream.

I have here a FPGA behind PCIe which exports SRAM which I use for
pstore. Now it seems that the FPGA no longer supports cmpxchg based
updates and writes back 0xffâ\80¦ff and returns the same.  This leads to
crash during crash rendering pstore useless.
Since I doubt that there is much benefit from using cmpxchg() here, I am
dropping this atomic access and use the spinlock based version.

Cc: Anton Vorontsov <anton@enomsg.org>
Cc: Colin Cross <ccross@android.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Rabin Vincent <rabinv@axis.com>
Tested-by: Rabin Vincent <rabinv@axis.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
[kees: remove "_locked" suffix since it's the only option now]
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Willy Tarreau <w@1wt.eu>
fs/pstore/ram_core.c