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drm/i915: Unify CHICKEN_PIPESL_1 register definitions
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 5 Mar 2014 11:05:47 +0000 (13:05 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 5 Mar 2014 20:30:44 +0000 (21:30 +0100)
commit8f670bb15a69e1186098454beb1b43dc1d923a24
tree175f076b4559206efa56e321ca74c165950f0ab7tree | snapshot (tar.gz zip)
parent2adb6db8d9fb0f94173a4cba6e1dcb8585f1a928commit | diff
drm/i915: Unify CHICKEN_PIPESL_1 register definitions

We have two names for the same register CHICKEN_PIPESL_1 and
HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one.

Also rename the FBCQ disable bit to resemble the name we've
given to a similar bit on earlier platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | blame | history
drivers/gpu/drm/i915/intel_pm.c diff | blob | blame | history