clk: Consolidate recalc rate logic
authorStephen Boyd <sboyd@codeaurora.org>
Wed, 26 Mar 2014 23:06:36 +0000 (16:06 -0700)
committerMike Turquette <mturquette@linaro.org>
Wed, 30 Apr 2014 18:51:48 +0000 (11:51 -0700)
commit8f2c2db132cf5f4ffb4b9702ddb7e6bc5a343814
tree3cbf9723124a52478c2cb424abf1705a5d0240e0
parent86a612349fa58467cd63b30748114ec377d61807
clk: Consolidate recalc rate logic

The same if-else statement exists four times to recalculate the
rate of a clock. Consolidate this logic into a single function to
save some lines.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/clk.c