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(parent: eee8f78) | patch
clk: st: Add polarity bit indication
authorGabriel FERNANDEZ <gabriel.fernandez@st.com>
Tue, 15 Jul 2014 15:20:25 +0000 (17:20 +0200)
committerMike Turquette <mturquette@linaro.org>
Tue, 29 Jul 2014 05:36:44 +0000 (22:36 -0700)
commit8f26df843204a5f24254fdf2836bd81202d8e929
tree423e505c8aabf60cb288602ebcbef0c436bf9c73tree | snapshot (tar.gz zip)
parenteee8f783277ae1c174350e6048b1352a997421e5commit | diff
clk: st: Add polarity bit indication

This patch introduces polarity indication for pll power up bit
and for standby bit in order to have same code between stih416
and stih407 boards.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/st/clkgen-fsyn.c diff | blob | blame | history