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(parent: 83a3c22) | patch
gpu: host1x: mipi: Fix clock lane register for DSI
authorThierry Reding <treding@nvidia.com>
Wed, 8 Apr 2015 15:06:08 +0000 (17:06 +0200)
committerThierry Reding <treding@nvidia.com>
Thu, 13 Aug 2015 11:47:16 +0000 (13:47 +0200)
commit8ed5c0623272663783e052123fea02651464a0a5
tree54b8e1415d9187d5093a4669c7cf714553a1facctree | snapshot (tar.gz zip)
parent83a3c223cc5678c5ced554fa2819747fd53437c7commit | diff
gpu: host1x: mipi: Fix clock lane register for DSI

Use more consistent names for the clock lane configuration registers and
fix the offset of the upper clock lane configuration register for the
first DSI pad.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/host1x/mipi.c diff | blob | blame | history