MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.
authorRalf Baechle <ralf@linux-mips.org>
Mon, 22 Mar 2010 23:02:43 +0000 (00:02 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 12 Apr 2010 16:26:19 +0000 (17:26 +0100)
commit8d9df29db273ab9a330828f4f4f6669d293a730a
tree7f5e9c87125d53fc2a512be150b01f6116918b3f
parent9538ca636f2fa28ae1514327328e2869f0215981
MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.

Previously it was unconditionally used on all Sibyte family SOCs.  The
M3 bug has to be handled in the TLB exception handler which is extremly
performance sensitive, so this modification is expected to deliver around
2-3% performance improvment.  This is important as required changes to the
M3 workaround will make it more costly.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mach-sibyte/war.h
arch/mips/sibyte/sb1250/setup.c