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(parent: 9d971b3) | patch
drm/i915: Use PIPE_CONTROL for flushing on gen6+.
authorJesse Barnes <jbarnes@virtuousgeek.org>
Sun, 16 Oct 2011 08:23:31 +0000 (10:23 +0200)
committerKeith Packard <keithp@keithp.com>
Thu, 20 Oct 2011 22:26:41 +0000 (15:26 -0700)
commit8d31528703ceda6f631e39953130abe9b3ca52b2
treef64ff55c111adb9e479cad97ceede6174b824aa6tree | snapshot (tar.gz zip)
parent9d971b37534fb268251f74cc04a36a0a16f7da04commit | diff
drm/i915: Use PIPE_CONTROL for flushing on gen6+.

v2 by danvet: Use a new flag to flush the render target cache on gen6+
(hw reuses the old write flush bit), as suggested by Ben Widawsdy.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
[danvet: this seems to fix cairo-perf-trace hangs on my snb]
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
drivers/gpu/drm/i915/i915_reg.h diff | blob | blame | history
drivers/gpu/drm/i915/intel_ringbuffer.c diff | blob | blame | history