pwm: mediatek: Disable clock on PWM configuration failure
authorZhi Mao <zhi.mao@mediatek.com>
Fri, 30 Jun 2017 06:05:20 +0000 (14:05 +0800)
committerThierry Reding <thierry.reding@gmail.com>
Mon, 21 Aug 2017 08:39:11 +0000 (10:39 +0200)
commit8bdb65dc8575978214785462870852a56b6a21ac
treefb421e982b77d6e0afae2e3fc8f7217e4af4093c
parent62843a6152e7c19f28c368bb51cac1bbfcdf4249
pwm: mediatek: Disable clock on PWM configuration failure

Make sure to disable the PWM clock if the PWM cannot be configured due
to the clock divider exceeding the maximum value.

While at it, replace the hardcoded maximum clock divider with a defined
constant to improve code readability.

Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
drivers/pwm/pwm-mediatek.c