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(parent: 7adbeda) | patch
MIPS: Read watch registers with interrupts disabled.
authorDavid Daney <ddaney@caviumnetworks.com>
Mon, 5 Jan 2009 23:29:58 +0000 (15:29 -0800)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 30 Jan 2009 21:32:58 +0000 (21:32 +0000)
commit8bc6d05b481aa7dc79c81b8ffac0da755e149643
tree0c6b7c62dbec9d598546c7e58cb13c0c78212a1etree | snapshot (tar.gz zip)
parent7adbedaf4469dcdcd6a1ab9bdeb8ad854d4f9827commit | diff
MIPS: Read watch registers with interrupts disabled.

If a context switch occurred between the watch exception and reading the
watch registers, it would be possible for the new process to corrupt their
state.  Enabling interrupts only after the watch registers are read avoids
this race.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/genex.S diff | blob | blame | history
arch/mips/kernel/traps.c diff | blob | blame | history