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(parent: fd73caa) | patch
drm/tegra: dpaux: Registers are 32-bit
authorThierry Reding <treding@nvidia.com>
Tue, 2 Jun 2015 11:13:01 +0000 (13:13 +0200)
committerThierry Reding <treding@nvidia.com>
Fri, 12 Jun 2015 14:26:04 +0000 (16:26 +0200)
commit8a8005e3e19915559b542bf85cc1b17024ee1d31
tree4bb8b985a8c62ad80e531d8aa393a368546510fftree | snapshot (tar.gz zip)
parentfd73caa5e72f0fcf9732b18d123eead96286fd5bcommit | diff
drm/tegra: dpaux: Registers are 32-bit

Use a sized unsigned 32-bit data type (u32) to store register contents.
The DPAUX registers are 32 bits wide irrespective of the architecture's
data width.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/dpaux.c diff | blob | blame | history