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(parent: 8e8e523) | patch
drm/radeon/kms: fix up DP clock programming on DCE4/5
authorAlex Deucher <alexdeucher@gmail.com>
Fri, 20 May 2011 08:34:17 +0000 (04:34 -0400)
committerDave Airlie <airlied@redhat.com>
Fri, 20 May 2011 10:02:22 +0000 (20:02 +1000)
commit86a94defe2b88380c28547d7053633b26a397d42
tree5f18745f77235b364f85c8b74804957b285cca4etree | snapshot (tar.gz zip)
parent8e8e523d865490e95ed7c9d2e173c02648d6be90commit | diff
drm/radeon/kms: fix up DP clock programming on DCE4/5

In DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
depending on the asic.  The crtc virtual pixel clock is derived from
the DP ref clock.

- DCE4: PPLL or ext clock
- DCE5: DCPLL or ext clock

Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
PPLL/DCPLL programming and only program the DP DTO for the
crtc virtual pixel clock.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/radeon/atombios_crtc.c diff | blob | blame | history
drivers/gpu/drm/radeon/radeon_encoders.c diff | blob | blame | history