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clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider
authorTomasz Figa <t.figa@samsung.com>
Fri, 20 Dec 2013 22:58:38 +0000 (07:58 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Fri, 20 Dec 2013 22:58:38 +0000 (07:58 +0900)
commit86576fbe201b7617e9dc689df0e5df0807acdd30
treec24f9da39e2d6f9a61bd070a87b4fd0bf238c508tree | snapshot (tar.gz zip)
parenta98e3190fc7dbb6157ef51ce8d92a36b06d282bbcommit | diff
clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider

The clock was missing CLK_SET_RATE_PARENT flag, which caused rate
setting failures due to inability of reconfiguration of second
divider behind it.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
drivers/clk/samsung/clk-exynos4.c diff | blob | blame | history