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clk: sunxi-ng: gate: Support common pre-dividers
authorChen-Yu Tsai <wens@csie.org>
Tue, 14 Feb 2017 03:35:23 +0000 (11:35 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Mon, 6 Mar 2017 09:25:56 +0000 (10:25 +0100)
commit845d6b0ff92d2c8151892c81f2050b873d7a7ef7
tree873f001cee80840bf6f9185c2aa239e01ddedf95tree | snapshot (tar.gz zip)
parent9ad0bb39fce319d7b92c17d306ed0a9f70a02e7dcommit | diff
clk: sunxi-ng: gate: Support common pre-dividers

Some clock gates have a pre-divider between the source input and the
gate itself. A notable example is the HSIC 12 MHz clock found on the
A83T, which has the 24 MHz main oscillator as its input, and a /2
pre-divider.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu_gate.c diff | blob | blame | history