drm/i915/bdw: Use scratch page table for GEN8 PPGTT
authorBen Widawsky <benjamin.widawsky@intel.com>
Sat, 8 Mar 2014 19:58:16 +0000 (11:58 -0800)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 11 Mar 2014 20:05:49 +0000 (21:05 +0100)
commit8407bb9129da95fc4099b84cdbbc23e6d4f66aee
treec42f882b58dbcc9a2980f22735079c125ebc4a9f
parent6c7fba04ecfddd634751239a52df0eccffc8700b
drm/i915/bdw: Use scratch page table for GEN8 PPGTT

I'm not clear if the hardware is still subject to the same prefetching
issues that made us use a scratch page in the first place. In either
case, we're using garbage with the current code (we will end up using
offset 0).

This may be the cause of our current gem_cpu_reloc regression with
PPGTT. I cannot test it at the moment.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_gem_gtt.c