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iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS_OPS condition
authorBaptiste Reynal <b.reynal@virtualopensystems.com>
Wed, 4 Mar 2015 15:51:06 +0000 (16:51 +0100)
committerJoerg Roedel <jroedel@suse.de>
Mon, 23 Mar 2015 14:21:26 +0000 (15:21 +0100)
commit83a60ed8f0b5ce550afd5802b60468578db4e055
tree9794a804ce571a32042363c983aa00a3d9c3c7a7tree | snapshot (tar.gz zip)
parentbc465aa9d045feb0e13b4a8f32cc33c1943f62d6commit | diff
iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS_OPS condition

This patch is a fix to "iommu/arm-smmu: add support for iova_to_phys
through ATS1PR".
According to ARM documentation, translation registers are optional even
in SMMUv1, so ID0_S1TS needs to be checked to verify their presence.
Also, we check that the domain is a stage-1 domain.

Signed-off-by: Baptiste Reynal <b.reynal@virtualopensystems.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/arm-smmu.c diff | blob | blame | history