usb: dwc3: Add SoftReset PHY synchonization delay
authorThinh Nguyen <Thinh.Nguyen@synopsys.com>
Fri, 16 Mar 2018 22:33:48 +0000 (15:33 -0700)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 25 May 2018 14:17:39 +0000 (16:17 +0200)
commit7fb2d2f1b04d983cb8b92ac12c6a15bd905943b2
treef2cbdcefaf0a48b95dffb89987be68babd987d0e
parent81ba08e69fe2af23162c4222ddd67622895f5bac
usb: dwc3: Add SoftReset PHY synchonization delay

[ Upstream commit fab3833338779e1e668bd58d1f76d601657304b8 ]

>From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
bit is cleared, we must wait at least 50ms before accessing the PHY
domain (synchronization delay).

Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/usb/dwc3/core.c