iommu/amd: Adding Extended Feature Register check for PC support
authorSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Fri, 1 Apr 2016 13:05:57 +0000 (09:05 -0400)
committerJoerg Roedel <jroedel@suse.de>
Thu, 7 Apr 2016 11:29:40 +0000 (13:29 +0200)
commit7d7d38afb3e8fdfebfd867cc0ff4b5c45c14053c
tree215acef518b3b70a3e1e79db103ed9e094ec8321
parent9735a22799b9214d17d3c231fe377fc852f042e9
iommu/amd: Adding Extended Feature Register check for PC support

The IVHD header type 11h and 40h introduce the PCSup bit in
the EFR Register Image bit fileds. This should be used to
determine the IOMMU performance support instead of relying
on the PNCounters and PNBanks.

Note also that the PNCouters and PNBanks bits in the IOMMU
attributes field of IVHD headers type 11h are incorrectly
programmed on some systems.

So, we should not rely on it to determine the performance
counter/banks size. Instead, these values should be read
from the MMIO Offset 0030h IOMMU Extended Feature Register.

Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/amd_iommu_init.c