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clk: samsung: exynos7: Correct nr_clk_ids for fsys0
authorAlim Akhtar <alim.akhtar@samsung.com>
Wed, 26 Aug 2015 03:30:43 +0000 (09:00 +0530)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Tue, 15 Sep 2015 09:00:08 +0000 (11:00 +0200)
commit7cca2e0744a990bfa0ae93a40c886fd589fb37b7
tree6f76869da28053596796dd69a812b6b8ba1214c2tree | snapshot (tar.gz zip)
parentcfc7588a310254b659cb0a6fcca1fffd3f223090commit | diff
clk: samsung: exynos7: Correct nr_clk_ids for fsys0

This patch corrects the nr_clk_ids for fsys0 block
which is wrongly set to number of clocks of the TOP1 CMU.
This also adjusts the gate clocks order.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
drivers/clk/samsung/clk-exynos7.c diff | blob | blame | history