ALSA: AACI: allow writes to MAINCR to take effect
authorRussell King <rmk+kernel@arm.linux.org.uk>
Sat, 5 Feb 2011 10:41:55 +0000 (10:41 +0000)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Mon, 7 Feb 2011 15:15:26 +0000 (15:15 +0000)
commit7c289385b84d136089b8a1149321ebffa5193595
tree2d591872a86dfa7f042371501d014e54e3ecda50
parentec11594fbd5a3d2a47a7a7eda6d076363b78957c
ALSA: AACI: allow writes to MAINCR to take effect

The AACI TRM requires the MAINCR enable bit to be held zero for two
bitclk cycles plus three apb_pclk cycles.  Use a delay of 1us to
ensure this.

Ensure that writes to MAINCR to change the addressed codec only happen
when required, and that they take effect in a similar manner to the
above, otherwise we seem to occasionally have stuck slot busy bits.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
sound/arm/aaci.c