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(parent: c7ead11) | patch
drm/nvc0/ltcg: mask off intr 0x10
authorBen Skeggs <bskeggs@redhat.com>
Wed, 26 Sep 2012 02:43:10 +0000 (12:43 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 26 Sep 2012 02:43:10 +0000 (12:43 +1000)
commit79eee7aa0d4de5a42331c63d3c7c735248b53d0c
tree6c5cd081e1d2181d4f9ef3ac33481e3e049ec80atree | snapshot (tar.gz zip)
parentc7ead11d0b498984169871fd03c57441862ec3f3commit | diff
drm/nvc0/ltcg: mask off intr 0x10

NVIDIA do that at startup too on Fermi, so perhaps the heap of 0x10
intrs we receive are normal and we can ignore them.

On Kepler NVIDIA *don't* do this, but the hardware appears to come up
with the bit masked off by default - so that's probably why :)

This should silence some interrupt spam seen on Fermi+ boards.

Backported patch from reworked nouveau kernel tree.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvc0_fb.c diff | blob | blame | history