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MIPS: Fix TLBR-use hazards for R2 cores in the TLB reload handlers
authorRalf Baechle <ralf@linux-mips.org>
Thu, 20 Jun 2013 12:56:17 +0000 (14:56 +0200)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 21 Jun 2013 16:07:03 +0000 (18:07 +0200)
commit73acc7df534ff458a81435178dab3ea037ed6d78
tree7e6f7c7af7ccbeb81224eb88bc17d498fa529290tree | snapshot (tar.gz zip)
parentb90b3802624e1f2a509f3e9f39775d94ec4762d7commit | diff
MIPS: Fix TLBR-use hazards for R2 cores in the TLB reload handlers

MIPS R2 documents state that an execution hazard barrier is needed
after a TLBR before reading EntryLo.

Original patch by Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/5526/
arch/mips/mm/tlbex.c diff | blob | blame | history