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pinctrl: uniphier: support 3-bit drive strength control
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Tue, 31 May 2016 08:05:14 +0000 (17:05 +0900)
committerLinus Walleij <linus.walleij@linaro.org>
Tue, 31 May 2016 10:46:18 +0000 (12:46 +0200)
commit72e5706aa786f6640b229717b7d9d537058c59cf
tree8e14a67f1e887411ac0dbdcd5daa139b18eeb3c4tree | snapshot (tar.gz zip)
parent9eaa98a63c8a34a807ba95e384aacd28fa60ddd9commit | diff
pinctrl: uniphier: support 3-bit drive strength control

The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive
strength control.  Drive strength of some pins are controlled by
3-bit width registers (8-level granularity).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c diff | blob | blame | history
drivers/pinctrl/uniphier/pinctrl-uniphier.h diff | blob | blame | history