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clk: sunxi-ng: A31: Fix spdif clock register
authorMarcus Cooper <codekipper@gmail.com>
Tue, 20 Dec 2016 10:44:46 +0000 (11:44 +0100)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Mon, 2 Jan 2017 21:24:55 +0000 (22:24 +0100)
commit70421257c068b91476e70cade15fca68045d0693
tree7745d2742b1e803ffdc3676136701d46c01714d0tree | snapshot (tar.gz zip)
parentbb021cda2ccf45ee9470bf0f8c55323ad1c761aecommit | diff
clk: sunxi-ng: A31: Fix spdif clock register

As the SPDIF was rarely documented on the earlier Allwinner SoCs
it was assumed that it had a similar clock register to the one
described in the H3 User Manual.

However this is not the case and it looks to shares the same setup
as the I2S clock registers.

Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu-sun6i-a31.c diff | blob | blame | history