i2c: piix4: Avoid race conditions with IMC
authorRicardo Ribalda <ricardo.ribalda@gmail.com>
Wed, 11 Jan 2017 09:11:44 +0000 (10:11 +0100)
committerWolfram Sang <wsa@the-dreams.de>
Thu, 12 Jan 2017 19:52:12 +0000 (20:52 +0100)
commit701dc207bf551d9fe6defa36e84a911e880398c3
tree7ec8b3ac8cd6431cbf19bc88b1ec273ed87a10f2
parent2659161dd40dbb599a19f320164373093df44a89
i2c: piix4: Avoid race conditions with IMC

On AMD's SB800 and upwards, the SMBus is shared with the Integrated
Micro Controller (IMC).

The platform provides a hardware semaphore to avoid race conditions
among them. (Check page 288 of the SB800-Series Southbridges Register
Reference Guide http://support.amd.com/TechDocs/45482.pdf)

Without this patch, many access to the SMBus end with an invalid
transaction or even with the bus stalled.

Reported-by: Alexandre Desnoyers <alex@qtec.com>
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>:
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
drivers/i2c/busses/i2c-piix4.c