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MIPS: kernel: {ftrace,kgdb}: Set correct address limit for cache flushes
authorLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Mon, 16 Dec 2013 12:06:55 +0000 (12:06 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 26 Mar 2014 22:09:18 +0000 (23:09 +0100)
commit6ebda44f366478d1eea180d93154e7d97b591f50
tree88a32637a7ad46a690692a3603b369c4f9485515tree | snapshot (tar.gz zip)
parentde8974e3f76c00231cf6839797b4766d5a926ca3commit | diff
MIPS: kernel: {ftrace,kgdb}: Set correct address limit for cache flushes

When flushing the icache, make sure the address limit is correct
so the appropriate 'cache' instruction will be used. This has no
impact on cores operating in non-eva mode. However, when EVA is
enabled, we ensure that 'cache' will be used instead of 'cachee'.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
arch/mips/kernel/ftrace.c diff | blob | blame | history
arch/mips/kernel/kgdb.c diff | blob | blame | history
Motorola kernel-slsi